Bryan Ackland

School: Schaefer School of Engineering & Science
Department: Electrical and Computer Engineering
Building: Burchard Building
Room: 211
Phone: 201-216-8096

      May 1979        Ph.D. Electrical Engineering, University of Adelaide, South Australia. Thesis Dissertation: “Cache Store Concepts in Small High Speed Computers”

      May 1975        B.E. (First Class Honors) in Electrical Engineering, University of Adelaide, South Australia.

      May 1972        B.Sc. in Physics, Flinders University, South Australia

Institutional Service

2012 to Present

Distinguished Service Professor, Electrical & Computer Engineering Dept., Stevens Institute of Technology, Hoboken NJ. (full-time)


Adjunct Professor, Electrical & Computer Engineering Dept., Stevens Institute of Technology, Hoboken NJ. (part-time)


Professional Service

2004 to 2010

Vice President Engineering, Noble Peak Vision, Wakefield MA. Assembled and led engineering team to successfully develop and test VGA CMOS imagers using monolithic Ge-on-Si photo-detectors for night vision applications. Responsibilities included pixel design, analog signal path and novel double-CDS scheme that eliminated both kTC and pixel flicker noise. Developed automatic exposure control software that implemented concurrent AGC, exposure (integration) time and DC iris control.

2000 to 2003:

Vice President, Circuits & Systems Research, Agere Systems, Murray Hill NJ. Led a team of 75 Ph.D. level researchers in developing new circuit and systems technology for a communications semiconductor company. Technology focus included digital, analog and RF circuit design, media and communication signal processing, hardware and software processor architecture, data networking, optical communications systems and VLSI design methodology.

1986 to October 2000:

Director of DSP & VLSI Systems Research Department at Bell Laboratories, Lucent Technologies, Holmdel NJ. Recruiting, management and overall direction of a group of approximately 15 Ph.D. level Principal Investigators plus technical support staff conducting research in the areas of VLSI architectures, signal processing algorithms, MOS circuit design and CAD tools for full custom VLSI design. Contributions in mixed signal circuits for gigabit SONET and Ethernet  transceivers, VLSI architectures for ATM and IP switching, bus based multiprocessor architectures for DSP Systems on a Chip (SoC), low power architectures and circuits for equalization and coding, and active pixel CMOS cameras.

1978 to 1986:

Member of Technical Staff in Research at AT&T Bell Laboratories. Research interests spanned Expert Systems, CAD for VLSI, Digital MOS Circuits, MOS Simulation, Special Purpose Processor Architectures, Raster Graphics and Multiprocessor Systems. Contributions in Expert Systems, CAD for Custom VLSI, Digital MOS Circuits, MOS Simulation, Raster Graphics and Multiprocessor Systems.

Honors & Awards

Henry Morton Distinguished Tesaching Professor, Stevens Institute of Technology, Spetember 2015

Best Panel Award for “Are Startups Killing Innovation” at IEEE Solid State Circuits Conference, Feb. 2001.

Best Paper in IEEE Journal of Solid State Circuits, 1998

Bell Laboratories Fellow 1993 for "Leadership in full custom VLSI tools and circuits."

Exceptional Achievement in Technical Communication given by Society for Technical Communication 1993.

IEEE Fellow 1992 for "Contributions to the design of custom integrated circuits and signal processing systems."

Best Paper Award at IEEE International Conf. on Computer Design, October 1985.


Professional Societies

Administrative Committee of IEEE Solid State Circuits Society, 2001-2015.

Executive Committee of IEEE International Solid State Circuits Conference, 2001-2015.

Executive Committee of IEEE/ACM Design Automation Conference, 1997-2003.

General Chair, 39th IEEE/ACM Design Automation Conference, 2002.

Patents & Inventions
  1. 8,686,365         “Imaging Apparatus and Methods”, April 2014.
  2. 8,648,948         “Imaging Systems with Multiple Imaging Pixel Types and Related Methods”, Feb. 2014.
  3. 8,634,008         “Image Signal Processing Methods and Apparatus”, Jan. 2014.
  4. 8,586,907         “Methods of Operating an Imaging Pixel to Accumulate Charge from a Photocurrent”, Nov. 2013.
  5. 8,294,100         “Imaging Apparatus and Methods”, Oct. 2012.
  6. 8,084,739         “Imaging Apparatus and Methods”, Dec.  2011.
  7. 8,072,525         “Imaging Signal Processing Methods and Apparatus”, Dec. 2011.
  8. 8,063,422         “Image Detection Apparatus and Methods”, Nov. 2011.
  9. 8,022,350         “Imaging Pixel Comprising a Comparator to Compare Integrated Photocurrent to a Reference Value and Digital Output Circuitry”, Sept 2011.
  10. 7,528,357         “Pulse detector which employs a self-resetting pulse amplifier”, May 2009.
  11. 7,326,903         "Mixed analog and digital pixel for high dynamic range readout", Feb. 2008.
  12. 6,150,922         “Serial Communication Technique”, Nov. 2000
  13. 6,141, 050        “MOS Image Sensor”, Oct., 2000
  14. 6,097,195         “Methods and Apparatus for Increasing Metal Density in an Integrated Circuit while also Reducing Parasitic Capacitances”. Aug., 2000
  15. 5,987,156         “Apparatus for Correcting Fixed Column Noise in Images Acquired By A Fingerprint Sensor”, Nov., 1999
  16. 5,835,141         “Single Polysilicon CMOS Active Pixel Image Sensor, Oct., 1998
  17. 5,739,562         “Combined photogate and photodiode active pixel image sensor”, April 1998
  18. 5,604,705         “Static random access memory sense amplifier”, Feb. 1997
  19. 5,576,763         "Single-Polysilicon CMOS Active Pixel," Nov. 1996
  20. 5,541,402         "Imaging Active Pixel Device Having A Non-Destructive Read-Out Gate", July 1996
  21. 5,220,325         "Hierarchical Variable Length Decoder for Digital Video Data," June 1993
  22. 4,509,187         "Time Warp Signal Recognition Processor Using Recirculating and/or Reduced Array of Processor Cells," May 1985.
  23. 4,412,313         "Random Memory Access System Having High-Speed Serial Data Paths," Oct. 1983.
  24. 4,384,273         "Time Warp Signal Recognition Processor for Matching Signal Patterns," May 1983
Selected Publications
Conference Proceedings
  1. Inglis, D., Manchanda, L, Comizzoli, R., Dickinson, A., Martin, E., Mendis, S., Silverman, P., Weber, G, Ackland, B. and O'Gormon, L.. (Feb 1998). "A Robust 1.8V 250mW Direct Contact 500 dpi Fingerprint Sensor", IEEE Solid State Circuits Conference, San Francisco, CA.. 284-285.
  2. Ackland, B., Rafferty, C., King, C., Aberg, I., O'Neill, J., Sriram, T., Lattes, A., Godek, C. and Pappas, S.. (Jun 2009). "A Monolithic Ge-on-Si CMOS Imager for Short Wave Infrared", International Image Sensor Workshop, Bergen, Norway.
  3. Aberg, I., Ackland, B., Beach, J., Johnson, R., King, C., Lattes, A., O'Neill, J., Pappas, S., Sriran, T., and Rafferty, C.. (Dec 2010). "A Low Dark Current and High Quantum Efficiency Monolithic Germanium-on-Silicon CMOS Imager Technology for Day and Night Imaging Applications", IEEE International Electron Device Meeting, San Francisco, CA.
  1. O'Neill, J., Ackland, B., Rao, S. and Hatamian, M.. (Mar 1993). "A 200 MHz CMOS Broadband Switching Chip", IEEE Journal Solid State Circuits, 28 (3), 269-275.
  2. Loinaz, M., Singh, K., Blanksby, A., Inglis, D., Azadet, K. and Ackland, B.. (Feb 1998). "A 200mW, 3.3V CMOS Color Camera IC Producing 352x288 24b Video at 30 Frames/s", IEEE Journal Solid State Circuits, 33 (12), 2092-2103.
  3. Ackland, B., Anesko, A., Brinthaupt, D., Daubert, S., Kalavade, A., Knobloch, J., Micca, E., Motrui, M., Nicol, C., O'Neill, J., Othmer, J., Sackinger, E., Singh, K., Sweet, J., Terman, C., and Williams, J.. (Mar 2000). "A Single-chip 1.6-billion 16-b MAC/s Multiprocessor DSP", IEEE Journal Solid State Circuits, 35 (3), 412-424.
  • CPE 690 Introduction to VLSI Design
  • EE 471 Transport Phenomena in Solid State Devices
  • CPE 390 Microprocessor Systems
  • CPE 487 Digital System Design